1. Field of the Invention
The present invention relates to a receiving module and a receiver having the same and, more particularly, to a receiving module which is applicable to a parallel link operating at a high speed of more than Giga bit per second (Gbps) and is robust against intersymbol interference (ISI), timing jitter, and voltage noise, and a receiver having the same.
2. Discussion of Related Art
As a transmission rate of information bits is increased, chip-to-chip communication is more sensitive to interference, distortion and timing uncertainty.
That is, since a ratio of a timing uncertainty region to a bit time increases at a higher transmission rate, the communication has smaller data eye opening and is more sensitive to intersymbol interference (ISI) and clock jitter.
The intersymbol interference is caused by limited bandwidth of an electrical conductor such as a coaxial cable or a twisted pair cable, and the jitter represents uncertainty or error of a clock cycle which exists unavoidably by thermal noise and power supply noise.
FIG. 1 shows that a zero crossing point of a received waveform becomes ambiguous and a transition region thereof becomes wider as a data transmission rate increases relative to channel bandwidth.
Referring to FIG. 1, when a square wave stream, i.e., bit stream is transmitted, a waveform of a received signal maintains a square wave “as is” even after the bit stream passes through an ideal channel, i.e., electric conductor.
However, since channels practically have distortion and noise, the waveform of the received signal is in the form of a bit stream having a fluent transition region, not a perfect square wave stream.
Such phenomenon appears to be noticeable at a higher data transmission rate. That is, the transition region is wider, and the zero crossing point is more ambiguous. Thus, it is difficult to properly restore data even with sampling of each bit at its central region.
For the foregoing reason, data may be restored more efficiently by detecting a difference between a previous bit and a current and enlarging the difference instead of sampling it at a predetermined accurate location.
A concept of detecting a difference between the two bits or direction to restore the original signal has been already introduced, and the present invention is focused on a high speed receiver integrated circuit of a new structure capable of efficiently implementing the concept.
With a proper length of approximately tens of meters, it may be more efficient in cost, power consumption, and a board area to transmit a signal via an electric conductor instead of an optical fiber cable.
However, in the case where the electric conductor is employed in a local area network (LAN), a connection of a computer to peripheral devices or the like to transmit a signal at a high speed of more than several Giga bit per second (Gbps), the receiver that is robust against the interference or the timing jitter is required. The use of the receiver which is robust against the interference or the timing jitter reduces a low bit error rate, thereby realizing reliable signal transmission.